Senior Wireless SoC Engineer/Manager
October 2017 – present
Apple, Cupertino, California,
Principal Engineer/Manager
February 1997 – September 2017
QUALCOMM, INC. San Diego/Santa Clara, California,
• Hardware Lead for Modem and SoC level architecture, design and integration of Modem Subsystems in 8 generations of Qualcomm’s MSM & MDM ASIC’s, including the last 5 of Qualcomm’s Multimode 3G/ 4G Modem Subsystems.
• Architect driving decisions on SoC level tradeoffs such as performance vs area vs power or localized vs. central power control
• Technical Manager supervising the work of several small teams of Digital Design and Verification Engineers in located in San Diego and Santa Clara
• Chip Lead for a team of Digital Design, Digital Verification and Physical Design Engineers working on the SoC architecture, low level design, implementation and successful tape-out of Qualcomm’s first combined 3G / 4G wireless communication digital modem baseband System-on-Chip (MDM9600), a first in the industry
• Line Manager responsible for leading and mentoring of at present 7 direct level reports
• Extensive experience working with geographically distributed design team across multiple locations (Austin, TX & East Coast, Farnborough U.K, Haifa, Israel, as well as Bangalore, India)
• In charge of high level design and digital integration for MDM Family of System-On-Chip ASICs centered around various 3G/4G Digital Baseband Modems, Processors and supporting hardware blocks
• Lead the pre-silicon power estimation and post silicon power debug / validation efforts for multiple generations of Modem / SoC designs
• Advanced the development and deployment of a set of design methodologies for IP protection and technology abstraction, leading to increased reuse of internal IP’s
• Involved in the high level design and integration of major subsystems inside various MSM Family System-On-Chip ASICs using in-house (Baseband Modems, Digital Signal Processors & Multimedia Engines) and 3rd Party (ARM cores, USB peripherals etc.) IP blocks
• Contributed to the definition, high level design, implementation and validation of bus, boot, power and security architecture in several advanced mobile wireless ASIC’s
• Developed several receive & transmit physical layer baseband modem blocks for CDMA2000 1xRTT, IS-856 1xEVDO and UMTS WCDMA air interface as modem hardware block designer
• Definition and implementation of high speed / high performance, AMBA AHB & AXI based Bus Architectures including, bus bridges, arbiters, decoders and FIFO's
• Integration of ARM7 - ARM11, Cortex M3, A5/A7 and proprietary DSP's in System-On-Chip Designs with supporting blocks such as internal sRAMs & ROMs and Interrupt Controllers
• Working experience with memory controllers for LPDDR, NAND and NOR FLASH
• System integration of high performance wireless peripherals such as 2G/3G and 4G WWAN modems as well as wired peripherals such as SPI, SLIMBus, USB, SDIO & PCIe
•Definition & design of common System-on-Chip block such as Clock & Reset Controllers, GPIO Muxing Blocks and General Purpose DMA Controllers
•Extensive experience with low power design techniques at the system level such as global / local clock gating, dynamic voltage scaling and local power island collapse
• Verilog, VHDL, Perl, TCL & other scripting languages, C / C++
• VLSI ASIC Design flow & tools, emphasis on low power RTL implementations (including 90, 65, 45, 28, 20 and most recently 14nm technology process node)
• Extensive working experience with EDA Design & Verification tools: Mentor Modelsim/Questa, Synopsis Design Compiler & PrimeTime / PTPX, Cadence Conformal & Conformal Low Power, Atrenta Spyglass
(pending) – System and method for Bus Bandwidth Management in a system on a chip
7,319,852 - Apparatus and method for DC offset compensation in a direct conversion receiver
6,975,584 - Communication system method and apparatus
6,847,677 - Method and apparatus for efficient Walsh covering and summing of signals in a communication system
6,763,492 - Method and apparatus for encoding of linear block codes
6,714,599 – Method and apparatus for efficient processing of signal in a communication system
Nikolai Schlegel et.al, Usage of Conformal Low Power on high performance / low power ASICs combining Modem & Multimedia functionality, CDN Live 2007 conference
Pushkin Kachroo, Nikolai Schlegel, Joseph A. Ball, John S. Bay, Image Processing Based Control for Scaled Automated Vehicles, (ITSC-00179), for ITSC'97 IEEE conference.
January 1996 – January 1997
CENTER FOR TRANSPORTATION RESEARCH, Blacksburg, Virginia
Developed the image recognition based control software for a model autonomous vehicle. Accomplished the goal of the vehicle steering itself by following the highway markings in the processed images taken by a small camera on the vehicle itself
September 1994 – July 1995
INSTITUTE FOR TECHNICAL MECHANICS, Braunschweig, Germany
Developed software to measure torque and force by image processing
August 2002 – December 2003
UNIVERSITY OF CALIFORNIA SAN DIEGO EXTENSION, San Diego, CA
Developed the material for and taught the VHDL course at the UCSD Extension program
• VHDL / Verilog, C / C++ / SystemC, ARM Assembly, Perl, Python & Shell Scripting
• Operating Systems: UNIX/Linux/MacOSX, Windows & Embedded Proprietary OS
Post-Graduate courses in Systems Engineering
September 2000 – May 2002
UNIVERSITY OF SOUTHERN CALIFORNIA, Los Angeles, CA
Master of Science in Electrical Engineering, Overall GPA: 3.81/4.0
August 1995 - December 1996
Thesis: Automatic lateral vehicle control using image processing.
VIRGINIA POLYTECHNIC INSTITUTE & STATE UNIV. Blacksburg, VA
Undergraduate Studies in Electrical Engineering for a total of 8 semesters
"Vordiplom" in September 1993 with grade "Gut" (good)
October 1991 - May 1995
TECHNISCHE UNIVERSITÄT BRAUNSCHWEIG, Braunschweig, Germany